The present invention relates to probe cards for testing unsevered integrated circuits formed on a semiconductor wafer. More particularly, the present invention relates to high density probe cards for testing very large scale integrated circuits having a multiplicity of connection pads with which connection must be made to conduct the testing.
Integrated circuits are typically formed on a semiconductor substrate by a series of processes involving the formation or deposition of a three dimensional pattern of metallic, insulating or semiconductor material on a major surface thereof. Connections to the integrated circuitry of the pattern are typically made at metallic connection pads formed at the periphery of the pattern. In the completed product, fine wires are used to connect these pads to pins of a carrier, such as a dual in-line package. Mounting of the integrated circuit die in a carrier and attachment of the fine wires is a time-consuming, labor intensive, expensive step in the process of manufacturing useable integrated circuits.
In order to achieve economies of volume, integrated circuits are formed as an array of substantially identical, replicated circuits on thin wafers of crystalline material, such as crystalline silicon. These wafers are typically four to eight inches in diameter. Before the individual circuit dies are severed from the wafer, each die is tested to be sure that it meets the specifications of the integrated circuit it embodies. This essential testing is carried out by apparatus employing probe cards.
The wafer is mounted on a moveable wafer stage, and a probe card, having an array of minute, spaced apart electrical probe needles, or probes, is brought into planar registration with the connection pads of each integrated circuit pattern formed on the wafer. Electrical conditions are then applied through the probes to the pads of the integrated circuit and the response of the circuit to appropriate electrical test conditions is then measured, also through the probes. If the circuit meets its specification, it is passed. If the circuit is defective, it is marked with a small drop of ink or paint, and ultimately it is discarded. By testing each circuit before it is severed from the die, only those circuits which are operational and meet the specification will continue in the manufacturing process.
Integrated circuit technology has now developed very high density circuits referred to as very large scale integration or VLSI. These circuits combine many thousands of transistor elements into a very small die. For example, with five mil centers for pads, and with 64 pads per edge, it is now possible to form a VLSI die having 256 to 320 peripheral connection pads with a minimum edge length of 320 mils. In practice, the pads on each edge are arranged in a staggered, two row "checkerboard" pattern. A hitherto unsolved need has arisen to provide a probe card having a density sufficiently high to test these new VLSI circuits on the wafer before they are severed into individual circuit dies.
The difficulty of providing as many as 256 to 320 probes in a probe card is not trivial. There are many parameters which must be carefully observed. These include:
Alignment. The alignment of a probe card (also known as "X-Y" positioning) is the degree of accuracy with which a probe contacts the specified target area of the integrated circuit's connection pad. This area is typically the center of the pad.
Probe Force. Probe force is the amount of force exerted on the metallic (aluminum) connection pad by the probe. Probe force is a function of the taper length, probe diameter, probe angle, and probe length to the location of securement at the support ring.
Overdrive. Overdrive is the amount of travel in the Z (height) direction of the probe card assembly after the first probe of the probe array has contacted the circuit pattern.
Contact Force. Contact force is the amount of force per square mil of area of the contact surface of the probe tip per mil of overdrive. Contact force is measured in grams per square mil per mil of overdrive.
Balanced Contact Force. It is important that the contact force with which each probe of the probe card array contacts each respective pad of the integrated circuit is substantially the same throughout the probe array. If the contact force from probe to probe is not substantially the same, the contact ohmic resistance from probe to probe will be different. If the contact ohmic resistance from probe to probe is different, the signal integrity throughout the probe array will not be uniform. Balanced contact force is especially important in testing sensitive integrated circuits which are designed to function at high speeds.
Scrub. Scrub is the distance the probe tip moves in the "Y" direction after its first contact with the connection pad to the designated overdrive. Scrub actually scrapes the connection pad and cuts through any thin coating of aluminum oxide or glass residue from the fabrication process.
Contact Resistance. Contact Resistance is the resistance which occurs between the probe tip and the connection pad of the integrated circuit. The amount of contact resistance, measured in ohms, is a function of the composition of the probe, the composition of the metal pad being probed, the area of the contact surface of the probe tip and the probe force.
Planarization. Planarization of a probe card (also known as "Z" or height positioning) is the height positioning of the probe tips with respect to each other. A probe card is considered in planarization when all probes make electrical contact within a specified amount of overdrive travel between the first and last probes to make contact. Theoretically, a probe card is in perfect planarization if all probes make electrical contact at precisely the same time. Typically, a probe card is considered to be in planarization if there exists no more than 1.0 mil of overdrive travel between the first and last probes to make contact.
Several prior concepts have been proposed to solve the unique problems associated with high density probe cards for testing VLSI circuits. These prior concepts and approaches are summarized in the following discussion and illustrated in FIGS. 1 through 6 hereof. To facilitate clarity in understanding, similar elements are referred to in this specification with the same reference numeral.
One prior concept is to form an epoxy ring printed circuit probe card 30 with a set 32 of probes which are connected e.g. by solder 34 to conductive traces 36 formed on the bottom 38 of the card 30, as shown in FIGS. 1 and 2. An annular anodized aluminum ring 40 carries a cured shoulder formation 42 of epoxy resin which embeds and thereby aligns and secures the probes 32 in proper orientation and position. As shown in FIGS. 1 and 2, the probes 32 have a beam region or length 32a as measured from the inner wall 45 of the epoxy formation 42 to the probe taper or point 32b which is disposed at a predetermined angle relative to the horizontal, typically about seven degrees (7.degree.). After the probe array comprising the aluminum ring 40, shoulder 42 and probe set 32 is preformed on a precise alignment fixture it is installed in an annular central opening 44 of the printed circuit card 30 and secured in place by a suitably curable epoxy resin 46. The prior art probe card 30 is generally in accordance with the disclosure of U.S. Pat. No. 3,905,098, for example.
A second prior concept, illustrated in FIG. 3, attempted to achieve higher density by combining the FIG. 1-2 approach with a second set 48 of probes connected to traces 50 formed on the top 52 of the card 30a by solder connections 54. After the first set 32 of probes is installed on the card 30, the second set 48 of probes is then installed by a second epoxy region 56 to the card 30a above the conventional probe ring 40.
The second approach as illustrated in FIG. 3 has a number of drawbacks: it is difficult to construct. It will not easily meet the criteria for acceptable probe cards discussed above. For example, the probe tips 48b of the second set 48 attack the pads of the VLSI circuit at a much sharper angle than do the probes of the first set 32. The sharper angle of the beam region 48a of the second set 48 greatly increases the contact force applied to the pad, and reduces the amount of scrub.
The contact force of the probes 48a will be different than the contact force of the probes 32a; hence, balanced contact force throughout the entire probe array is difficult to achieve. Planarization and alignment are also very difficult to achieve with the FIG. 3 approach, absent a highly complex fabrication fixture.
Another prior concept, illustrated by FIG. 4, calls for two sets of probes on the card, with a conventional probe array set 32 on the bottom 38 and with an array of probe-holding blades 58 connecting from printed circuit traces 50a on the upper surfaces to probes 60 held by the blades 58 near the VLSI chip, as diagrammed in the FIG. 4 sectional view. The probe needle holding blades 58 may be of the type described in U.S. Pat. No. 3,849,728, and may be soldered to the traces 50a along metalized lower edges as shown in FIG. 4.
If the blades 58 are made of metal, significant problems arise with the increase in capacitive coupling between probes such blade structures present. If the blades 58 are made of ceramic, they are very brittle and difficult to handle. Moreover, ceramic has proven unreliable because of the alignment and planarization problems introduced by the differences in coefficients of expansion between the ceramic or metal blade 58 and the tungsten probe wire 60, solder 62 and printed circuit trace materials 50a. It will be appreciated that the solder bead 62 required to secure the blade 58 to its corresponding trace 50a is vastly more elongated and extensive than the solder beads 36 used to connect each lower probe wire 32 to its corresponding lower trace 34.
One other significant drawback of the FIG. 4 approach is that the substantially shorter beam lengths of the probes 60 make the establishment of balanced contact force throughout the overall probe array more difficult.
Yet another prior concept, illustrated diagrammatically in FIG. 5, requires the use of two printed circuit boards, a so-called mother boards 30c, and a so-called daughter board 30d. The mother board 30c carries the outer set of probes 63 in conventional fashion, and the daughter board 30d carries the inner set of probes 64. The daughter board 30d fits into an annular recess 68 formed in the mother board 30c, and a series of flexible conductive traces, held in place by a foam compression gasket 70 (metal on erastma) interconnect traces 72 on the top of the daughter board 30d to corresponding conductive traces 74 on the top of the mother board 30c. An annular frog ring 73 supports the mother board 30c and is itself connected mechanically to an upper test card 30e. Pogo pins 76 provide electrical connections between traces on the lower surface of the test card 30e and the traces 74 of the mother board 30c. An inner annular housing 78 holds the daughter board 30d and the foamed connector 70 in place against the mother board 30c. An inner flange 80 of the frog ring 73 retains the inner housing 78 in place.
One drawback of the multiple printed circuit board solution is its complexity. Another drawback is that the compression connection 70 may not prove to be reliable. A further drawback is that if impedance matching both sets of probes to a nominal impedance, such as 50 ohms or 93 ohms, the two standard impedances followed in the probe card industry. One other significant drawback is that the inner housing 78 makes it impossible to add certain needed circuit elements, preferably to the top of the daughter board 30d. These elements are typically small bypass capacitors, which are added to the probe arrays in the vicinity of the inner annular opening 44.
The FIG. 5 arrangement additionally suffers from the significant drawback that the probe force applied by each of the probes 64 of the inner set is difficult to balance with the force applied by each of the probes 63 of the outer set.
Yet one more prior concept probe card 30f is illustrated in the FIG. 6A-6B drawing pair. This prior concept follows the concept outlined in connection with FIGS. 1 and 2, except that a higher density is achieved by staggering the probes of the probe array. The probes 32 are arranged into a lower row 32c and an upper row 32d which is offset radially and interleaved with the lower row 32c. The probe wires 32e extend radially outwardly to traces 34a on the lower surface 38 of the probe card 30f.
The drawback and ultimate density limitation for the probe card 30f is that the traces 34a are formed on the same lower surface 38 and must be located at the same radial distance. The single set of traces carry all of the connections for all of the probes 32. In order for there to be sufficient spacing for 256 to 320 radial traces 34a, they must be radially spaced from the central opening a sufficent distance to allow for minimum trace width and for insulative spacing between the traces. This means that the traces 34a are set back so far that the probe wires 32e extend a considerable distance in very close proximity. This close proximity leads directly to shorts and to undesirable coupling and electrical cross-talk between the probes.
The probing equipment, the test head and its interface hardware dictate the size of the probe card to be used for testing the integrated circuit. More specifically, the test head and the test head interface hardware dictate the outer radial distances to which the probe traces can extend. These outer radial distances in turn limit the number of probe traces and the amount of space between those traces on a give circumference. With the limited size of the probe card and the limited radial distances of the probe traces from center, and with the resultant closeness of adjacent traces, it is extremely difficult to construct a high density probe card of the type illustrated in FIGS. 6A and 6B, due to the liklihood that adjacent probe wires, especially those at the corners of the integrated circuit, will contact one another and become shorted. This is especially true with a rectangular integrated circuit layout, or a square layout for an integrated circuit whose connection pads are not necessarily uniformly distributed along the sides.